1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a metal line of a semiconductor device and a method of forming the same.
2. Description of the Related Art
A related art method of manufacturing a semiconductor device will be described below with reference to FIGS. 1A and 1B.
Referring to FIG. 1A, a first interlayer insulation layer 110 is formed on a substrate 100. The first interlayer insulation layer 110 is etched to form a via hole and a trench. Then, a first via hole and a first metal line 120 are formed by filling the via hole and the trench with a metal. The first metal line 120 and the first interlayer insulation layer 110 are planarized using a chemical mechanical polishing (CMP) process.
Meanwhile, when the ductility of the metal line 120 is high, scratch 130 often occurs in the surface of the planarized metal line. Specifically, when the metal line is formed of copper (Cu), the scratch 130 occurs much more.
Referring to FIG. 1B, a second interlayer insulation layer 115 is formed by depositing a dielectric material on the first metal line 120 and the first interlayer insulation layer 110.
The second interlayer insulation layer 115 is etched to form a via hole and a trench. Then, a second via plug and a second metal line 140 are formed by filling the via hole and the trench with a second metal.
Since the second interlayer insulation layer 115 is formed along the scratch 130 formed on the surface of the first metal line 120, the scratch 130 causes the formation of notch on the surface of the second interlayer insulation layer 115.
Accordingly, in forming the second metal line 140, a remained metal 145 is formed in the notch, as well as in the via hole and the trench region.
However, the remained metal 145 has a problem that shorts the second metal lines 140.
Also, the shorting due to the remained metal 145 degrades the yield of the semiconductor device.